1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly, to a non-volatile semiconductor memory device of storing a plurality of pieces of information using different charge trapping regions in a charge trapping layer, in which a memory cell is composed of a MOS transistor having a charge trapping layer in a gate dielectric layer.
2. Description of the Related Art
Non-volatile semiconductor memory devices have been widely applied to information systems and communications systems because of their capability of holding memory information even when power source is switched off. Among them, a flash EEPROM (EEPROM: Electrically Erasable Programmable ROM, hereinafter referred to as a flash memory) performs an erase operation with respect to the whole chip or on a block-by-block basis, thereby reducing the size of each memory cell and achieving low cost. Therefore, there is a rapidly increasing demand for the flash memory.
Examples of a memory cell applicable to the flash memory include a memory cell with a double-layer polysilicon structure which is composed of a floating gate and a control gate, a memory cell composed of a MOS transistor having a charge trapping layer in a gate dielectric layer (hereinafter referred to as a MONOS memory cell), and the like. Among them, the MONOS memory cell is characterized in that one memory cell has two different regions each storing information, thereby making it possible to achieve low cost and large capacity, and that miniaturization is easily achieved. Therefore, those having the MONOS memory cell have become a mainstream flash memory (see, for example, U.S. Pat. No. 6,011,725).
In the flash memory having the MONOS memory cell, information is read from one of the two regions by, for example, comparing a magnitude of a read reference current output from a reference cell having the same structure as that of the memory cell with a magnitude of a memory cell current output from the one region of the memory cell.
When a program operation has been performed with respect to the memory cell, the memory cell has current characteristics such that a threshold value is shifted while holding current characteristics similar to current characteristics of the memory cell in an erased state. Therefore, by setting the read reference current output from the reference cell to have characteristics such that a threshold value is shifted while holding current characteristics equivalent to those of the memory cell current, an optimal reference can be created.
In this read operation, if the read reference current is set to be a mean current between a current of the memory cell in an information-erased state and a current of the memory cell in an information-programmed state, a difference between the reference current and the memory cell current in the erased state and a difference between the reference current and the memory cell current in the programmed state are equal to each other. Therefore, a margin between a program operation and a read operation can be maximized.
However, the MONOS memory cell has a specific effect that the memory cell current characteristics of one of the regions is affected by a state of the other region (hereinafter referred to as a second bit effect) (see, for example, U.S. Pat. No. 6,643,170).
For example, when, after information is set into one of the regions, information is programmed into the other region, the memory cell current characteristics of the one region vary. Therefore, in the case where the reference current is set as described above, the difference between the reference current and the memory cell current in the erased state and the difference between the reference current and the memory cell current in the programmed state are different from each other. The second bit effect is not dependent of a physical position of the charge trapping region in the memory cell, and is such that a state of a bit previously set is affected by a state of a bit written later.
As described above, in conventional non-volatile semiconductor memory devices having the MONOS memory cell, the memory cell current characteristics vary due to the second bit effect, so that the difference between the reference current and the current in each memory state is reduced, resulting in a small operation margin when information is read. Particularly, when a plurality of memory states are achieved by changing the amount of trapped charge to store multi-bit information, the reduction of the operation margin due to the influence of the second bit effect is significant.
Also, in the case of the MONOS memory cell, a predetermined range of voltage is applied to the memory cell, and therefore, in order to avoid the influence of the second bit effect, the reference current might be optimized in the vicinity of a middle of the applied voltage range, depending on the variation due to the second bit effect. In this case, however, the read margin is decreased in a lower limit portion and an upper limit portion of the voltage range.
Therefore, in conventional non-volatile semiconductor memory devices having the MONOS memory cell, it is difficult to achieve multi-bit memory. Even in a binary MONOS memory cell, if an operation margin is small, it is difficult to achieve a low-voltage operation.